Analog-to-digital converters (ADCs) with signal bandwidth (BW)>500 MHz and Signal to Noise and Distortion Ratio (SNDR)>60 dB are needed for many applications, such as: base station receivers, automotive ethernet, and next generation 5G cellular telecommunications. Sigma-Delta modulation is a method for encoding analog signals into digital signals, often used in an analog-to-digital converter (ADC) and capable of achieving these performance levels. Sigma-Delta modulation is also used to transfer high bit-count, low frequency, digital signals into lower bit-count, higher frequency, digital signals as part of the process to convert digital signals into analog (i.e. as part of a digital-to-analog converter (DAC)). Sigma-delta ADCs are oversampling ADCs that sample the signal at much higher rates than a Nyquist rate.
In a conventional ADC, an analog signal is integrated, or sampled, with a sampling frequency and subsequently quantized in a multi-level quantizer into a digital signal. This process introduces quantization error noise. The first step in a sigma-delta modulation is delta modulation. In delta modulation the change in the signal (i.e. its ‘delta’) is encoded, rather than the absolute value. The result is a stream of pulses, as opposed to a stream of numbers, as is the case with pulse code modulation. In sigma-delta modulation, the accuracy of the modulation is improved by passing the digital output through a 1-bit DAC and adding (sigma) the resulting analog signal, to the input signal (the signal before delta modulation), thereby reducing the error introduced by the delta-modulation.
Discrete-time ADCs implemented using switched-capacitor circuits have been the designer's choice for the last few decades. However, recently, continuous-time sigma-delta ADCs have gained popularity in technical journals and the industry. Continuous-time sigma-delta ADCs with multi-bit quantization are popular for bandwidths (BW) larger than 100 MHz. Multi-bit quantization has the advantages of lower quantization noise, relaxed clock jitter requirement, and it allows the designers to use more aggressive noise transfer functions (NTFs). The principle of noise shaping and oversampling in continuous-time sigma-delta ADCs remains the same as its discrete-time counterpart. The key difference between a continuous-time sigma-delta ADC and a discrete time sigma-delta ADC is where the sampling operation takes place. In the continuous-time design, input sampling takes place just before the quantizer. The loop filter is now continuous-time using continuous-time integrators, often resistor-capacitor (RC) or transconductance-capacitor (gm/C) integrators.
Continuous-time sigma-delta ADCs contain one or multiple sigma-delta modulators (SDMs). A SDM is a feedback loop containing a loop filter, the quantizer, and the feedback DAC(s). The function of the quantizer is sampling and quantization. Its input signal is continuous in time domain and continuous in voltage (or current) domain, i.e. a continuous-time, continuous-value (analog signal). Its output signal should be discrete in time domain and discrete in voltage domain, i.e. discrete-time discrete-value (digital signal). The function of the main feedback DAC is a zero-order hold, which converts the digital signal to analog signal.
Excess loop delay (ELD) is a known phenomenon in continuous-time sigma-delta ADCs, as described in J. A. Cherry and W. M. Snelgrove, “Excess loop delay in continuous-time DeltaSigma modulators”, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 46, no. 4, pp. 376-389, April 1999. Generally, the loop delay contains the regeneration time of the quantizer, the delay of the feedback DACs and the delay of the circuit between the quantizer and DACs. For high-speed continuous-time Sigma-Delta ADCs, the excess loop delay can be as large as one quantizer sampling clock period (1 Ts). The excess loop delay can deteriorate the resolution of the continuous-time sigma-delta ADCs, or even make it unstable. One known technique to compensate the excess loop delay is to add a direct feedback path through an ELD DAC around the quantizer itself, as shown in FIG. 1.
Referring to FIG. 1, a block diagram of part of a continuous-time sigma-delta ADC 100 with quantization and ELD compensation is illustrated. The continuous-time sigma-delta ADC 100 includes an input signal 102 and whereby a main feedback signal 103 is subtracted from the input signal 102 in first summing junction 104. The resultant signal is input to a loop filter 106 and a feedback ELD compensation signal 117 subtracted therefrom in a second summing junction 108. The analog signal output from the second summing junction 108 is input to a quantizer 110, such as an ADC and input to a delay 112. The output of the delay 112 is the output 114 of the sigma-delta ADC 100. The output 114 is fed back 116 to an ELD DAC 118, to generate the ELD compensation signal 117 to be input to the second summing junction 108. The ELD compensation is typically implemented by a capacitive DAC and the capacitor of an RC integrator. The feedback 116 is also fed back to a main DAC 120 to generate an analog version of the output signal 114 to be input to first summing junction 104 and thereby form a feedback loop. Notably, an amplifier of the RC integrator is located in the fast (main) feedback loop. However, the amplifiers in the fast feedback loop have very high gain bandwidth (GBW) requirements and they are very power hungry.
Referring now to FIG. 2, a known example of a conventional SDM system architecture 200 with multi-bit quantization and ELD compensation is illustrated. Conventionally, the ELD DAC 118 has a voltage output, and the output of the loop filter 106 is also in the voltage domain. These two voltage signals are summed in summing junction 108, sometimes with a summation amplifier, as described in M. Bolatkale, L. Breems, R. Rutten and K. Makinwa, titled ‘A 4 GHz continuous-time ΔΣ ADC with 70 dB DR and −74 dBFS THD in 125 MHz BW’, published in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2857-2868, December 2011, or with passive components, as described in Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami and S. Korrapati, titled ‘A continuous-time 0-3 MASH ADC achieving 88 dB DR With 53 MHz BW in 28 nm CMOS’, published in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2868-2877, December 2014. The resultant output 209 from the summing junction 108 is the input voltage of the quantizer, which in this figure is shown as a multi-bit comparator Qin 210. Here, Qin 209 is compared with several reference voltages Vref1, Vref2, . . . , Vrefn 232 in several pre-amplifiers 234. The differences between Qin 209 and Vref1, Vref2, . . . , Vrefn 232 are amplified by the gain of the pre-amplifiers 234. These amplified signals are passed to respective latches 236, and are further amplified by the positive feedback of the latches 236. The outputs of the latches are the output of the multi-bit comparator 210. These outputs are sampled and passed to the main DAC 120 and ELD DAC 118 via feedback 116.
The loop filter can be in either feed-forward (FF) or feedback (FB) structure. Only one common fast FB path 250 is used for the ELD compensation. In the architecture of FIG. 2, if the total delay of the fast feedback path 250 through the multi-bit comparator 210 and ELD DAC 118 is less than a single sampling time period Ts (and the total delay of the slow feedback path through the multi-bit comparator 210 and the main DAC 120 is no more than one Ts), with proper parameters for the SDM, the SDM can be designed to be stable. In this scenario, a suitable resolution of the SDM can be achieved without use of the ELD loop. However, in a scenario of very high speed continuous-time Sigma-Delta ADCs, the pre-amplifiers 234 have to be optimized for less delay, which limits the gain they can offer, whilst consuming a lot of power. Also, the use of such preamplifiers 234 always creates undesirable delay.
Thus, there is a desire to reduce the effects of, or avoid, the delay introduced by such pre-amplifiers 234 in SDMs, and particularly continuous-time sigma-delta ADCs.